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HUF76423D3, HUF76423D3S Data Sheet October 1999 File Number 4707.2 20A, 60V, 0.037 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging JEDEC TO-251AA JEDEC TO-252AA Features * Ultra Low On-Resistance - rDS(ON) = 0.032, VGS = 10V - rDS(ON) = 0.037, VGS = 5V * Simulation Models - Temperature Compensated PSPICE(R) and SABER(c) Electrical Models - Spice and SABER(c) Thermal Impedance Models - www.Intersil.com * Peak Current vs Pulse Width Curve * UIS Rating Curve DRAIN (FLANGE) SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE HUF76423D3 HUF76423D3S Symbol D * Switching Time vs RGS Curves Ordering Information PART NUMBER PACKAGE TO-251AA TO-252AA BRAND 76423D 76423D HUF76423D3 HUF76423D3S G S NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF76423D3ST. Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified HUF76423D3, HUF76423D3S UNITS V V V A A A A Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTES: 60 60 16 20 20 20 20 Figure 4 Figures 6, 17, 18 85 0.567 -55 to 175 300 260 W W/oC oC oC oC 1. TJ = 25oC to 150oC. CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 1 CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures. UltraFETTM is a trademark of Intersil Corporation. PSPICE(R) is a registered trademark of MicroSim Corporation. SABER(c) is a Copyright of Analogy Inc. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 2000. HUF76423D3, HUF76423D3S Electrical Specifications PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVDSS IDSS IGSS VGS(TH) rDS(ON) ID = 250A, VGS = 0V (Figure 12) ID = 250A, VGS = 0V , TC = -40oC (Figure 12) Zero Gate Voltage Drain Current VDS = 55V, VGS = 0V VDS = 50V, VGS = 0V, TC = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A (Figure 11) ID = 20A, VGS = 10V (Figures 9, 10) ID = 20A, VGS = 5V (Figure 9) ID = 20A, VGS = 4.5V (Figure 9) THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA TO-251 and TO-252 1.76 100 oC/W oC/W TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 60 55 - - 1 250 100 3 0.032 0.037 0.040 V V A A nA VGS = 16V 1 - 0.027 0.031 0.033 V SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 30V, ID = 20A, Ig(REF) = 1.0mA (Figures 14, 19, 20) VDD = 30V, ID = 20A VGS = 10V, RGS = 10 (Figures 16, 21, 22) VDD = 30V, ID = 20A VGS = 4.5V, RGS = 10 (Figures 15, 21, 22) 12 145 27 50 240 120 ns ns ns ns ns ns SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance 1060 315 65 pF pF pF 28 16 1.2 3.5 7 34 20 1.5 nC nC nC nC nC 7 35 52 50 65 155 ns ns ns ns ns ns Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage SYMBOL VSD trr QRR ISD = 20A ISD = 10A Reverse Recovery Time Reverse Recovered Charge ISD = 20A, dISD/dt = 100A/s ISD = 20A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.0 90 225 UNITS V V ns nC 2 HUF76423D3, HUF76423D3S Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) 25 VGS = 10V ID, DRAIN CURRENT (A) 20 15 VGS = 4.5V 10 5 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101 SINGLE PULSE 0.01 10-5 10-4 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 500 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: IDM, PEAK CURRENT (A) 100 I = I25 175 - TC 150 VGS = 10V VGS = 5V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101 10 10-5 FIGURE 4. PEAK CURRENT CAPABILITY 3 HUF76423D3, HUF76423D3S Typical Performance Curves 300 IAS, AVALANCHE CURRENT (A) 100 (Continued) 200 ID, DRAIN CURRENT (A) 100 100s If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 10 STARTING TJ = 25oC 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TC = 25oC 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 1ms 10ms STARTING TJ = 150oC 1 1 0.01 0.1 1 10 100 100 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 5. FORWARD BIAS SAFE OPERATING AREA 60 50 ID, DRAIN CURRENT (A) 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VGS, GATE TO SOURCE VOLTAGE (V) TJ = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 60 50 40 30 VGS = 3.5V 20 10 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 3V VGS = 10V VGS = 5V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC VGS = 4V TJ = 175oC TJ = -55oC FIGURE 7. TRANSFER CHARACTERISTICS ID, DRAIN CURRENT (A) FIGURE 8. SATURATION CHARACTERISTICS 50 NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 40 ID = 20A ID = 10A 30 2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 VGS = 10V, ID = 20A 1.5 1.0 20 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) 0.5 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4 HUF76423D3, HUF76423D3S Typical Performance Curves 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.0 (Continued) 1.2 ID = 250A 1.1 0.8 1.0 0.6 0.4 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) 0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 10 VGS , GATE TO SOURCE VOLTAGE (V) 3000 CISS = CGS + CGD C, CAPACITANCE (pF) 1000 VDD = 30V 8 6 COSS CDS + CGD 100 CRSS = CGD VGS = 0V, f = 1MHz 1 10 60 4 WAVEFORMS IN DESCENDING ORDER: ID = 20A ID = 10A 0 5 10 15 20 25 30 2 0 20 0.1 Qg, GATE CHARGE (nC) VDS , DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 350 VGS = 4.5V, VDD = 30V, ID = 20A 300 SWITCHING TIME (ns) SWITCHING TIME (ns) tr 250 200 150 td(OFF) 100 50 td(ON) 0 0 10 20 30 40 50 tf 200 VGS = 10V, VDD = 30V, ID = 20A 150 td(OFF) 100 tf 50 tr td(ON) 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () RGS, GATE TO SOURCE RESISTANCE () FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE 5 Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS VDS RL VDD VDS VGS = 10V VGS + Qg(TOT) Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V DUT Ig(REF) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS VDS tON td(ON) RL VDS + tOFF td(OFF) tr tf 90% 90% VGS VDD DUT 0 10% 90% 10% RGS VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM 6 PSPICE Electrical Model .SUBCKT HUF76423 2 1 3 ; CA 12 8 1.46e-9 CB 15 14 1.46e-9 CIN 6 8 1.0e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD 10 rev 7 September 1999 LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 DRAIN 2 RSLC1 51 ESLC 50 RSLC2 5 51 ESG 6 8 + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 5.5e-9 LSOURCE 3 7 4.4e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 7.0e-3 RGATE 9 20 3.6 RLDRAIN 2 5 10 RLGATE 1 9 55 RLSOURCE 3 7 44 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.45e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3 S1A 12 S1B CA 13 + EGS 6 8 13 8 S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17 - - VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),3.5))} .MODEL DBODYMOD D (IS = 6.3e-13 RS = 6.8e-3 TRS1 = 1e-3 TRS2 = 1e-6 XTI = 4.3 CJO = 1.28e-9 TT = 5.1e-8 M = 0.5) .MODEL DBREAKMOD D (RS = 2.9e-1 TRS1 = 1e-4 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 9.5e-10 IS = 1e-30 N = 10 M = 0.82) .MODEL MMEDMOD NMOS (VTO = 2.10 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6) .MODEL MSTROMOD NMOS (VTO = 2.45 KP = 60.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.79 KP = 0.13 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 36 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.2e-3 TC2 = -5e-7) .MODEL RDRAINMOD RES (TC1 = 1.3e-2 TC2 = 3.1e-5) .MODEL RSLCMOD RES (TC1 = 5.5e-3 TC2 = 7e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -5.8e-6) .MODEL RVTEMPMOD RES (TC1 = -1.7e-3 TC2 = 8e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4.8 VOFF= -2.8) VON = -2.8 VOFF= -4.8) VON = -0.6 VOFF= 0.5) VON = 0.5 VOFF= -0.6) NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 7 + - EBREAK 11 7 17 18 66.0 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RDRAIN 21 16 DBODY MWEAK MMED RBREAK 18 RVTEMP 19 VBAT + 8 22 RVTHRES SABER Electrical Model REV 7 September 1999 template huf76423 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 6.3e-13, xti = 4.3, cjo = 1.28e-9, tt = 5.1e-8, m = 0.50) d..model dbreakmod = () d..model dplcapmod = (cjo = 9.5e-10, is = 1e-30, n = 10, m = 0.82 ) m..model mmedmod = (type=_n, vto = 2.10, kp = 6, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.45, kp = 60.5, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.79, kp = 0.13, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.8, voff = -2.8) DPLCAP sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.8, voff = -4.8) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.6, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.6) c.ca n12 n8 = 1.46e-9 c.cb n15 n14 = 1.46e-9 c.cin n6 n8 = 1.0e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 5.5e-9 l.lsource n3 n7 = 4.4e-9 GATE 1 RLGATE CIN LGATE RSLC2 ISCL LDRAIN 5 RLDRAIN RDBREAK 72 DBREAK 11 MWEAK MMED MSTRO 8 EBREAK + 17 18 71 RDBODY DRAIN 2 RSLC1 51 ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 DBODY m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.2e-3, tc2 = -5.0e-7 res.rdbody n71 n5 = 6.8e-3, tc1 = 1e-3, tc2 = 1e-6 res.rdbreak n72 n5 = 2.9e-1, tc1 = 1e-4, tc2 = 0 res.rdrain n50 n16 = 7.0e-3, tc1 = 1.3e-2, tc2 = 3.1e-5 res.rgate n9 n20 = 3.6 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 55 res.rlsource n3 n7 = 44 res.rslc1 n5 n51 = 1e-6, tc1 = 5.5e-3, tc2 = 7.0e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.45e-2, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.7e-3, tc2 = 8.0e-7 res.rvthres n22 n8 = 1, tc1 = -1.8e-3, tc2 = -5.8e-6 spe.ebreak n11 n7 n17 n18 = 66.0 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/100))** 3.5)) } } S1A 12 13 8 S1B CA 13 + EGS 6 8 S2A 14 13 S2B - LSOURCE 7 RLSOURCE SOURCE 3 RSOURCE RBREAK 17 18 RVTEMP CB + EDS 5 8 14 IT 19 15 VBAT + - - 8 RVTHRES 22 8 SPICE Thermal Model REV 1 September 1999 HUF76423T CTHERM1 th 6 1.40e-3 CTHERM2 6 5 8.30e-3 CTHERM3 5 4 7.00e-3 CTHERM4 4 3 3.20e-3 CTHERM5 3 2 1.50e-2 CTHERM6 2 tl 1.10 RTHERM1 th 6 1.20e-2 RTHERM2 6 5 2.99e-2 RTHERM3 5 4 8.43e-2 RTHERM4 4 3 4.73e-1 RTHERM5 3 2 7.14e-1 RTHERM6 2 tl 9.47e-2 RTHERM1 th JUNCTION CTHERM1 6 RTHERM2 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model SABER thermal model HUF76423T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 1.40e-3 ctherm.ctherm2 6 5 = 8.30e-3 ctherm.ctherm3 5 4 = 7.00e-3 ctherm.ctherm4 4 3 = 3.20e-3 ctherm.ctherm5 3 2 = 1.50e-2 ctherm.ctherm6 2 tl = 1.10 rtherm.rtherm1 th 6 = 1.20e-2 rtherm.rtherm2 6 5 = 2.99e-2 rtherm.rtherm3 5 4 = 8.43e-2 rtherm.rtherm4 4 3 = 4.73e-1 rtherm.rtherm5 3 2 = 7.14e-1 rtherm.rtherm6 2 tl = 9.47e-2 } 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl CASE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 9 |
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